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CDES
2008
90views Hardware» more  CDES 2008»
15 years 6 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
KES
2008
Springer
15 years 4 months ago
Incremental evolution of a signal classification hardware architecture for prosthetic hand control
Evolvable Hardware (EHW) is a new method for designing electronic circuits. However, there are several problems to solve for making high performance systems. One is the limited sca...
Jim Torresen
148
Voted
COMPSAC
2006
IEEE
15 years 8 months ago
A Service-Oriented Design Framework for Secure Network Applications
Abstract---Service Oriented Architecture (SOA) is an architectural style to reuse and integrate existing systems for designing new applications. Each application is designed in an ...
Hiroshi Wada, Junichi Suzuki, Katsuya Oba
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
15 years 11 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas
148
Voted
ECTEL
2007
Springer
15 years 11 months ago
Service-oriented Knowledge Architectures - Integrating Learning and Business Information Systems
This paper presents a dissertation project on business-integrated, service-oriented learning architectures. The isolation of corporate learning management from core business functi...
Katrina Leyking