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DATE
2009
IEEE
150views Hardware» more  DATE 2009»
15 years 12 months ago
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Sou...
143
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IJCNN
2008
IEEE
15 years 11 months ago
A neural wake-sleep learning architecture for associating robotic facial emotions
—A novel wake-sleep learning architecture for processing a robot’s facial expressions is introduced. According to neuroscience evidence, associative learning of emotional respo...
Chi-Yung Yau, Kevin Burn, Stefan Wermter
SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
15 years 11 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
15 years 11 months ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
GRAPHICSINTERFACE
2007
15 years 6 months ago
Constrained planar remeshing for architecture
Material limitations and fabrication costs generally run at odds with the creativity of architectural design, producing a wealth of challenging computational geometry problems. We...
Barbara Cutler, Emily Whiting