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» Formalizing Architectural Connection
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125
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DAC
2008
ACM
16 years 4 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
137
Voted
DAC
2007
ACM
16 years 4 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
DAC
2003
ACM
16 years 4 months ago
State-based power analysis for systems-on-chip
Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for ...
Reinaldo A. Bergamaschi, Yunjian Jiang
DAC
2003
ACM
16 years 4 months ago
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
DAC
2004
ACM
16 years 4 months ago
Quantum logic synthesis by symbolic reachability analysis
Reversible quantum logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability anal...
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Y...