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DAC
2006
ACM
16 years 4 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
FATES
2004
Springer
15 years 8 months ago
Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach
A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or ...
Behzad Bordbar, Kozo Okano
ICCAD
2000
IEEE
137views Hardware» more  ICCAD 2000»
15 years 7 months ago
Smart Simulation Using Collaborative Formal and Simulation Engines
computation and automatic abstraction. Second, Ketchum performs not only automatic test generation but also unreachability analysis, which enables the test generation effort to be ...
Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James ...
OTM
2005
Springer
15 years 8 months ago
Document Flow Model: A Formal Notation for Modelling Asynchronous Web Services Composition
This paper presents a formal notation for modelling asynchronous web services composition, using context and coordination mechanisms. Our notation specifies the messages that can b...
Jingtao Yang, Corina Cîrstea, Peter Henderso...
DAC
2003
ACM
16 years 4 months ago
Using a formal specification and a model checker to monitor and direct simulation
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
Serdar Tasiran, Yuan Yu, Brannon Batson