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DAC
2001
ACM
16 years 4 months ago
Semi-Formal Test Generation with Genevieve
This paper describes the first application of the Genevieve test generation methodology. The Genevieve approach uses semi-formal techniques derived from "model-checking"...
Julia Dushina, Mike Benjamin, Daniel Geist
ENTCS
2006
176views more  ENTCS 2006»
15 years 3 months ago
Automatic Formal Synthesis of Hardware from Higher Order Logic
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
Mike Gordon, Juliano Iyoda, Scott Owens, Konrad Sl...
HVC
2007
Springer
103views Hardware» more  HVC 2007»
15 years 9 months ago
Verifying Parametrised Hardware Designs Via Counter Automata
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of suc...
Ales Smrcka, Tomás Vojnar
CADE
2002
Springer
16 years 3 months ago
Formal Verification of a Java Compiler in Isabelle
This paper reports on the formal proof of correctness of a compiler from a substantial subset of Java source language to Java bytecode in the proof environment Isabelle. This work ...
Martin Strecker
ACSAC
1996
IEEE
15 years 7 months ago
Formal Techniques for an ITSEC-E4 Secure Gateway
In this paper we describe the method used to develop a gateway capable of meeting the ITSEC E4 requirements. The security policy was formally modelled and proven consistent with t...
Pierre Bieber