6581 search results - page 261 / 1317 » Formalizing Design Patterns |
131
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ICIP
2008
IEEE
16 years 5 months ago
2008
IEEE
The continual shrinkage of minimum feature size in integrated circuit (IC) fabrication incurs more and more serious distortion in the optical lithography process, generating circu...
144
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ISORC
1998
IEEE
15 years 8 months ago
1998
IEEE
Many engineers are still reluctant to adopt advanced object-oriented technologies (such as high modularity, dynamic binding, automatic garbage collection, etc.) for embedded syste...
112
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ATS
2009
IEEE
15 years 11 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
129
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DDECS
2006
IEEE
15 years 10 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
133
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ISCAS
1999
IEEE
15 years 8 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...