Platforms have become an important concept in the design of electronic systems. We present here the motivations behind the interest shown and the challenges that we have to face t...
Alberto L. Sangiovanni-Vincentelli, Luca P. Carlon...
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...
In this paper we propose new solution methods for designing tag sets for use in universal DNA arrays. First, we give integer linear programming formulations for two previous formal...
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...