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ITC
2002
IEEE
99views Hardware» more  ITC 2002»
15 years 11 months ago
Verifying Properties Using Sequential ATPG
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G....
EURODAC
1995
IEEE
195views VHDL» more  EURODAC 1995»
15 years 9 months ago
A hardware/software partitioning algorithm for pipelined instruction set processor
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi
WSC
2004
15 years 7 months ago
Automation of Human Decision Processes for Route Completion for Airspace Design Analysis
This paper describes an algorithm for approximating missing data in air traffic routes thereby allowing the lengths of different routes to be compared for our simulation analyses....
Lisa A. Schaefer
HIPEAC
2011
Springer
14 years 5 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
WCRE
2009
IEEE
16 years 27 days ago
SQUAD: Software Quality Understanding through the Analysis of Design
—Object-oriented software quality models usually use metrics of classes and of relationships among classes to assess the quality of systems. However, software quality does not de...
Foutse Khomh