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DATE
2006
IEEE
117views Hardware» more  DATE 2006»
15 years 8 months ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
ICCS
2007
Springer
15 years 6 months ago
Formal Verification of Analog and Mixed Signal Designs in Mathematica
In this paper, we show how symbolic algebra in Mathematica can be used to formally verify analog and mixed signal designs. The verification methodology is based on combining induct...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...
ISCAS
2003
IEEE
135views Hardware» more  ISCAS 2003»
15 years 7 months ago
Formal verification of LTL formulas for SystemC designs
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
Daniel Große, Rolf Drechsler
AOSE
2004
Springer
15 years 8 months ago
A Formal Approach to Design and Reuse Agent and Multiagent Models
While there are many useful models of agents and multi-agent systems, they are typically defined in an informal way and applied in an ad-hoc fashion. Consequently, multi-agent sys...
Vincent Hilaire, Olivier Simonin, Abder Koukam, Ja...
94
Voted
COMPSAC
2002
IEEE
15 years 7 months ago
Formalizing Incremental Design in Real-time Area: SCTL/MUS-T
Achievement of quality in software design, while never easy, is made more difficult by the inherent complexity of hard real-time (HRT) design. Furthermore, timing requirements in...
Ana Fernández Vilas, José J. Pazos A...