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CLUSTER
2000
IEEE
15 years 10 months ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 10 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
WOSP
2010
ACM
15 years 10 months ago
A framework for utility-based service oriented design in SASSY
The architecture of a software system has a significant impact on its quality of service (QoS) as measured by several performance metrics such as execution time, availability, th...
Daniel A. Menascé, John M. Ewing, Hassan Go...
CSB
2004
IEEE
158views Bioinformatics» more  CSB 2004»
15 years 10 months ago
Algorithms for Association Study Design Using a Generalized Model of Haplotype Conservation
There is considerable interest in computational methods to assist in the use of genetic polymorphism data for locating disease-related genes. Haplotypes, contiguous sets of correl...
Russell Schwartz
FPL
2006
Springer
125views Hardware» more  FPL 2006»
15 years 10 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt