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FDL
2005
IEEE
16 years 14 days ago
Integrating Model-Checking with UML-based SoC Development
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...
Peter Green, Kinika Tasie-Amadi
CODES
2000
IEEE
15 years 11 months ago
Automatic test bench generation for simulation-based validation
In current design practice synthesis tools play a key role, letting designers to concentrate on the specificationof the system being designed by carrying out repetitive tasks such...
Marcello Lajolo, Luciano Lavagno, Maurizio Rebaude...
186
Voted
PUC
2008
117views more  PUC 2008»
15 years 6 months ago
The disenchantment of affect
: In computing design, experience is often broken down, compartmentalized, and engineered: a process that often disenchants the original experience. In this paper, we demonstrate t...
Phoebe Sengers, Kirsten Boehner, Michael Mateas, G...
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
14 years 10 months ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa...
EVOW
2001
Springer
15 years 11 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...