178 search results - page 21 / 36 » Formally Specifying and Verifying Real-Time Systems |
144
click to vote
FDL
2007
IEEE
15 years 7 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
104
click to vote
ISSS
2000
IEEE
15 years 5 months ago
2000
IEEE
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness, New verification methods that o...
109
click to vote
STTT
2008
15 years 1 months ago
2008
Abstract. Managing access control policies in modern computer systems can be challenging and error-prone. Combining multiple disparate access policies can introduce unintended cons...
118
click to vote
ASE
2002
15 years 1 months ago
2002
This paper describes a specialized interface to PVS called TAME (Timed Automata Modeling Environment) which provides automated support for proving properties of I/O automata. A maj...
136
click to vote
CSFW
2005
IEEE
15 years 7 months ago
2005
IEEE
Availability is a critical issue in modern distributed systems. While many techniques and protocols for preventing denial of service (DoS) attacks have been proposed and deployed ...