Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
Henry M. Monti, Ali Raza Butt, Sudharshan S. Vazhk...
—Consider the following Simultaneous Message Passing (SMP) model for computing a relation f ⊆ X ×Y ×Z. In this model Alice, on input x ∈ X and Bob, on input y ∈ Y, send o...
User Interfaces for Mobile Processes Sonja Zaplata, Ante Vilenica, Dirk Bade, Christian P. Kunze Distributed Systems and Information Systems, Computer Science Department, Universit...
Sonja Zaplata, Ante Vilenica, Dirk Bade, Christian...