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» Framework Design for End-to-End Optimization
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TCAD
2008
119views more  TCAD 2008»
14 years 10 months ago
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
ATMOS
2010
128views Optimization» more  ATMOS 2010»
14 years 9 months ago
Robust Train Routing and Online Re-scheduling
Train Routing is a problem that arises in the early phase of the passenger railway planning process, usually several months before operating the trains. The main goal is to assign...
Alberto Caprara, Laura Galli, Leo G. Kroon, G&aacu...
INFOCOM
2010
IEEE
14 years 8 months ago
Throughput Analysis of Multiple Access Relay Channel under Collision Model
—Despite much research on the throughput of relaying networks under idealized interference models, many practical wireless networks rely on physical-layer protocols that preclude...
Seyed A. Hejazi, Ben Liang
GLVLSI
2009
IEEE
103views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Enhancing bug hunting using high-level symbolic simulation
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...
Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui ...
DAC
2009
ACM
15 years 11 months ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...