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» Framework Design for End-to-End Optimization
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DAC
2006
ACM
15 years 11 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
CORR
2008
Springer
105views Education» more  CORR 2008»
14 years 10 months ago
On Full Diversity Space-Time Block Codes with Partial Interference Cancellation Group Decoding
In this paper, we propose a partial interference cancellation (PIC) group decoding strategy/scheme for linear dispersive space-time block codes (STBC) and a design criterion for th...
Xiaoyong Guo, Xiang-Gen Xia
98
Voted
DAC
2009
ACM
15 years 11 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra
DAGSTUHL
2006
14 years 11 months ago
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
Douglas L. Maskell, Timothy F. Oliver
DAC
2003
ACM
15 years 11 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...