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    DATE
    1999
    IEEE
    120views Hardware» more  DATE 1999»
    FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
    15 years 2 months ago
    FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
    Download  www.cecs.uci.edu
    Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
    Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
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    68
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    JISE
    2000
    71views more  JISE 2000»
    Compact Test Generation Using a Frozen Clock Testing Strategy
    14 years 10 months ago
    Compact Test Generation Using a Frozen Clock Testing Strategy
    Download  www.iis.sinica.edu.tw
    Elizabeth M. Rudnick, Miron Abramovici
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