This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
Collaborative Virtual Environments (CVE) support the collaboration, communication and social interaction among users in virtual spaces. In this paper we present a customizable CVE...
Roberto C. Portugal, Luis A. Guerrero, David A. Fu...
A scalable architecture to facilitate emergent (self-organized) task decomposition using neural networks and evolutionary algorithms is presented. Various control system architectu...
Jekanthan Thangavelautham, Gabriele M. T. D'Eleute...
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwi...