990 search results - page 123 / 198 » From Design Patterns to Parallel Architectural Skeletons |
186
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GLVLSI
2011
IEEE
14 years 1 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
105
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FDL
2003
IEEE
15 years 3 months ago
2003
IEEE
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
CORR
2011
Springer
14 years 4 months ago
2011
Springer
We provide an overall description of the Ciao multiparadigm programming system emphasizing some of the novel aspects and motivations behind its design and implementation. An impor...
HPCA
2002
IEEE
15 years 10 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...