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» From Design Patterns to Parallel Architectural Skeletons
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PPOPP
2005
ACM
15 years 3 months ago
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir, A...
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
15 years 2 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
ASAP
2006
IEEE
97views Hardware» more  ASAP 2006»
15 years 3 months ago
Dynamic-SIMD for lens distortion compensation
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Ba...
ISPAN
2009
IEEE
15 years 4 months ago
Vector Bank Based Multimedia Codec System-on-a-Chip (SoC) Design
—In this paper, we present a design architecture of implementing a ”Vector Bank” into video encoder system, namely, an H.264 encoder, in order to detect and analyze the movin...
Ruei-Xi Chen, Wei Zhao, Jeffrey Fan, Asad Davari
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
15 years 2 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba