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» From Design Patterns to Parallel Architectural Skeletons
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HIPEAC
2005
Springer
15 years 3 months ago
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Abstract. Designers of large parallel computers and clusters are becoming increasingly concerned with the cost and power consumption of the interconnection network. A simple way to...
Pedro Javier García, Jose Flich, José...
HPCA
2007
IEEE
15 years 10 months ago
Illustrative Design Space Studies with Microarchitectural Regression Models
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
Benjamin C. Lee, David M. Brooks
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 3 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
FPGA
2008
ACM
163views FPGA» more  FPGA 2008»
14 years 11 months ago
TORCH: a design tool for routing channel segmentation in FPGAs
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
Mingjie Lin, Abbas El Gamal
DSD
2006
IEEE
131views Hardware» more  DSD 2006»
15 years 1 months ago
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
Christian Neeb, Norbert Wehn