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131
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HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
160
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HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
111
Voted
HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention tim...
171
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HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
136
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HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...