Sciweavers

570 search results - page 44 / 114
» From Program Verification to Program Synthesis
Sort
View
106
Voted
DAC
2005
ACM
16 years 3 months ago
IODINE: a tool to automatically infer dynamic invariants for hardware designs
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
Sudheendra Hangal, Naveen Chandra, Sridhar Narayan...
101
Voted
BIRTHDAY
2008
Springer
15 years 4 months ago
From Monadic Logic to PSL
One of the surprising developments in the area of program verification is how ideas introduced originally by logicians in the 1950s ended up yielding by 2003 an industrial-standard...
Moshe Y. Vardi
ASE
2010
129views more  ASE 2010»
15 years 2 months ago
Efficient monitoring of parametric context-free patterns
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Patrick O'Neil Meredith, Dongyun Jin, Feng Chen, G...
IJAIT
2006
106views more  IJAIT 2006»
15 years 2 months ago
An Empirical Evaluation of Automated Theorem Provers in Software Certification
We describe a system for the automated certification of safety properties of NASA software. The system uses Hoare-style program verification technology to generate proof obligatio...
Ewen Denney, Bernd Fischer 0002, Johann Schumann
156
Voted
FMCO
2009
Springer
130views Formal Methods» more  FMCO 2009»
15 years 8 days ago
Interleaving Symbolic Execution and Partial Evaluation
Partial evaluation is a program specialization technique that allows to optimize programs for which partial input is known. We show that partial evaluation can be used with advanta...
Richard Bubel, Reiner Hähnle, Ran Ji