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DSD
2007
IEEE
87views Hardware» more  DSD 2007»
15 years 3 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...
DAC
1995
ACM
15 years 1 months ago
Synthesis of Software Programs for Embedded Control Applications
— Software components for embedded reactive real-time applications must satisfy tight code size and runtime constraints. Cooperating finite state machines provide a convenient i...
Massimiliano Chiodo, Paolo Giusto, Attila Jurecska...
ICPR
2008
IEEE
15 years 10 months ago
Synthesis of large realistic iris databases using patch-based sampling
This paper presents a framework to synthesize large realistic iris databases, providing an alternative to iris database collection. Firstly, iris patch is used as a basic element ...
Tieniu Tan, Zhenan Sun, Zhuoshi Wei
FOSSACS
2010
Springer
15 years 4 months ago
Counting CTL
This paper presents a range of quantitative extensions for the temporal logic CTL. We enhance temporal modalities with the ability to constrain the number of states satisfying cert...
François Laroussinie, Antoine Meyer, Eudes ...
DAC
2006
ACM
15 years 10 months ago
SAT sweeping with local observability don't-cares
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
Qi Zhu, Nathan Kitchen, Andreas Kuehlmann, Alberto...