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MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
14 years 7 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
DSD
2003
IEEE
121views Hardware» more  DSD 2003»
15 years 2 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
ISCA
1996
IEEE
124views Hardware» more  ISCA 1996»
15 years 1 months ago
MGS: A Multigrain Shared Memory System
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale s...
Donald Yeung, John Kubiatowicz, Anant Agarwal
FCCM
2006
IEEE
100views VLSI» more  FCCM 2006»
15 years 3 months ago
Enabling a Uniform Programming Model Across the Software/Hardware Boundary
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single p...
Erik Anderson, Jason Agron, Wesley Peck, Jim Steve...
ISPASS
2010
IEEE
15 years 4 months ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...