Sciweavers

174 search results - page 27 / 35
» Functional Test Generation for Full Scan Circuits
Sort
View
TCAD
2002
134views more  TCAD 2002»
14 years 11 months ago
DS-LFSR: a BIST TPG for low switching activity
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
Seongmoon Wang, Sandeep K. Gupta
GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
15 years 5 months ago
The second harmonic generation case-study as a gateway for es to quantum control problems
The Second Harmonic Generation (SHG), a process that turns out to be a good test case in the physics lab, can also be considered as a fairly simple theoretical test function for g...
Ofer M. Shir, Thomas Bäck
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
15 years 5 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
96
Voted
ASPDAC
2004
ACM
112views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Longest path selection for delay test under process variation
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, We...
DAC
2002
ACM
16 years 17 days ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...