Sciweavers

174 search results - page 32 / 35
» Functional Test Generation for Full Scan Circuits
Sort
View
FPL
2001
Springer
96views Hardware» more  FPL 2001»
15 years 4 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
15 years 3 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
15 years 6 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...
BMCBI
2005
98views more  BMCBI 2005»
14 years 11 months ago
Iterative approach to model identification of biological networks
Background: Recent advances in molecular biology techniques provide an opportunity for developing detailed mathematical models of biological processes. An iterative scheme is intr...
Kapil G. Gadkar, Rudiyanto Gunawan, Francis J. Doy...
GLVLSI
1998
IEEE
124views VLSI» more  GLVLSI 1998»
15 years 3 months ago
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. ...