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» Functional Validation of Programmable Architectures
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103
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ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 17 days ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
144
Voted
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
15 years 10 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
124
Voted
CIIA
2009
15 years 4 months ago
Physical Synthesis for CPLD Architectures
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
Sid-Ahmed Senouci
125
Voted
IJNSEC
2007
137views more  IJNSEC 2007»
15 years 3 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
277
Voted

Book
7793views
17 years 1 months ago
Introduction to Neural Networks for C#
"Introduction to Neural Networks fpr C#, Second Edition, introduces the C# programmer to the world of Neural Networks and Artificial Intelligence. Neural network architectures...
Jeff Heaton