Sciweavers

1532 search results - page 146 / 307
» Functional density synchronization
Sort
View
78
Voted
CAV
2009
Springer
156views Hardware» more  CAV 2009»
15 years 4 months ago
Towards Performance Prediction of Compositional Models in Industrial GALS Designs
Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
Nicolas Coste, Holger Hermanns, Etienne Lantreibec...
ISSAC
2007
Springer
162views Mathematics» more  ISSAC 2007»
15 years 4 months ago
Multiprocessed parallelism support in ALDOR on SMPs and multicores
We report on a high-level categorical parallel framework, written in the Aldor language, to support high-performance computer algebra on symmetric multi-processors and multicore p...
Marc Moreno Maza, Ben Stephenson, Stephen M. Watt,...
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 2 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft
ICCAD
1999
IEEE
99views Hardware» more  ICCAD 1999»
15 years 2 months ago
FunState - an internal design representation for codesign
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components a...
Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Ro...
CAV
1999
Springer
92views Hardware» more  CAV 1999»
15 years 2 months ago
Latency Insensitive Protocols
The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of In...
Luca P. Carloni, Kenneth L. McMillan, Alberto L. S...