Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
Nicolas Coste, Holger Hermanns, Etienne Lantreibec...
We report on a high-level categorical parallel framework, written in the Aldor language, to support high-performance computer algebra on symmetric multi-processors and multicore p...
Marc Moreno Maza, Ben Stephenson, Stephen M. Watt,...
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components a...
The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of In...
Luca P. Carloni, Kenneth L. McMillan, Alberto L. S...