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HPCA
2000
IEEE
15 years 2 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
80
Voted
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 2 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
SSIAI
2000
IEEE
15 years 2 months ago
A New Bayesian Relaxation Framework for the Estimation and Segmentation of Multiple Motions
In this paper we propose a new probabilistic relaxation framework to perform robust multiple motion estimation and segmentation from a sequence of images. Our approach uses displa...
Alexander Strehl, Jake K. Aggarwal
ICCAD
1993
IEEE
101views Hardware» more  ICCAD 1993»
15 years 1 months ago
Convexity-based algorithms for design centering
A new technique for design centering, and for polytope approximation of the feasible region for a design are presented. In the rst phase, the feasible region is approximated by a ...
Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. K...
65
Voted
VLDB
1987
ACM
90views Database» more  VLDB 1987»
15 years 1 months ago
Index Access with a Finite Buffer
: A buffer is a main-memory area used to reduce accessto disks. The buffer holds pages from secondary storage files. A processrequesting a page causesa fault if the pageis not in t...
Giovanni Maria Sacco