Sciweavers

2076 search results - page 223 / 416
» Functional logic overloading
Sort
View
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
15 years 8 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
129
Voted
LORI
2009
Springer
15 years 8 months ago
Intentions and Assignments
Abstract. The aim of this work is propose a logical approach to intention dynamics based on the notion of assignment [7, 3]. The function of an assignment is to associate the truth...
Emiliano Lorini, Mehdi Dastani, Hans P. van Ditmar...
ICMCS
1999
IEEE
148views Multimedia» more  ICMCS 1999»
15 years 8 months ago
A System for the Fast Prototyping of Multidimensional Image Retrieval
Multidimensional image retrieval (MIR) views an image as a multidimensional object, where each dimension is a channel for retrieval. MIR has the potential of putting at work toget...
Carlo Meghini, Fabrizio Sebastiani, Umberto Stracc...
CSL
1999
Springer
15 years 8 months ago
Difference Decision Diagrams
This paper describes a new data structure, difference decision diagrams (DDDs), for representing a Boolean logic over inequalities of the form ¡£¢¥¤§¦©¨ and ¡¢¥¤Â...
Jesper B. Møller, Jakob Lichtenberg, Henrik...
ASPDAC
1998
ACM
92views Hardware» more  ASPDAC 1998»
15 years 8 months ago
A New Design for Double Edge Triggered Flip-flops
-- The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET fl...
Massoud Pedram, Qing Wu, Xunwei Wu