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SASP
2009
IEEE
222views Hardware» more  SASP 2009»
15 years 10 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
ISMVL
2009
IEEE
124views Hardware» more  ISMVL 2009»
15 years 10 months ago
Equivalence Checking of Reversible Circuits
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits’ primary inputs and outputs must be in pure logic states ...
Robert Wille, Daniel Große, D. Michael Mille...
PPDP
2009
Springer
15 years 10 months ago
Relational semantics for effect-based program transformations: higher-order store
We give a denotational semantics to a type and effect system tracking reading and writing to global variables holding values that may include higher-order effectful functions. Re...
Nick Benton, Andrew Kennedy, Lennart Beringer, Mar...
CODES
2007
IEEE
15 years 10 months ago
Secure FPGA circuits using controlled placement and routing
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...
Pengyuan Yu, Patrick Schaumont
GECCO
2007
Springer
138views Optimization» more  GECCO 2007»
15 years 10 months ago
Reducing the number of transistors in digital circuits using gate-level evolutionary design
This paper shows that the evolutionary design of digital circuits which is conducted at the gate level is able to produce human-competitive circuits at the transistor level. In ad...
Zbysek Gajda, Lukás Sekanina