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ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 10 months ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...
ISCAS
1999
IEEE
105views Hardware» more  ISCAS 1999»
15 years 10 months ago
Configuration self-test in FPGA-based reconfigurable systems
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for...
W. Quddus, Abhijit Jas, Nur A. Touba
FCCM
1998
IEEE
170views VLSI» more  FCCM 1998»
15 years 10 months ago
Characterization and Parameterization of a Pipeline Reconfigurable FPGA
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...
Matthew Moe, Herman Schmit, Seth Copen Goldstein
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
15 years 10 months ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
KBSE
1998
IEEE
15 years 10 months ago
Towards the Automated Debugging and Maintenance of Logic-based Requirements Models
In this paper we describe a tools environment which automates the validation and maintenance of a requirements model written in many-sorted first order logic. We focus on: a trans...
T. L. McCluskey, Margaret Mary West
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