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ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
15 years 7 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
TCAD
1998
125views more  TCAD 1998»
14 years 9 months ago
Test-point insertion: scan paths through functional logic
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
ICCAD
1997
IEEE
171views Hardware» more  ICCAD 1997»
15 years 2 months ago
The disjunctive decomposition of logic functions
In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...
Valeria Bertacco, Maurizio Damiani
ISMVL
2003
IEEE
125views Hardware» more  ISMVL 2003»
15 years 3 months ago
Compact Representations of Logic Functions using Heterogeneous MDDs
In this paper, we propose a compact representation of logic functions using Multi-valued Decision Diagrams (MDDs) called heterogeneous MDDs. In a heterogeneous MDD, each variable ...
Shinobu Nagayama, Tsutomu Sasao
INAP
2005
Springer
15 years 3 months ago
Using a Logic Programming Language with Persistence and Contexts
Abstract. This article merges two approaches: one dealing with persistence for logic programs, as provided by a relational database back-end and another which addresses the issues ...
Salvador Abreu, Vítor Nogueira