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CSREAESA
2006
15 years 4 months ago
Delay-Reduced Combinational Logic Synthesis using Multiplexers
- This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
Rekha K. James, T. K. Shahana, K. Poulose Jacob, S...
ESWA
2002
76views more  ESWA 2002»
15 years 3 months ago
Supporting software development through declaratively codified programming patterns
In current-day software development, programmers often use programming patterns to clarify their intents and to increase the understandability of their programs. Unfortunately, mo...
Kim Mens, Isabel Michiels, Roel Wuyts
MCMASTER
1993
15 years 7 months ago
A Taste of Rewrite Systems
Abstract. This survey of the theory and applications of rewriting with equations discusses the existence and uniqueness of normal forms, the Knuth-Bendix completion procedure and i...
Nachum Dershowitz
TCAD
2002
146views more  TCAD 2002»
15 years 2 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
TASE
2007
IEEE
15 years 9 months ago
Design of a Certifying Compiler Supporting Proof of Program Safety
Safety is an important property of high-assurance software, and one of the hot research topics on it is the verification method for software to meet its safety policies. In our p...
Yiyun Chen, Lin Ge, Baojian Hua, Zhaopeng Li, Chen...