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128
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ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
15 years 1 months ago
Reduction of interpolants for logic synthesis
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
John D. Backes, Marc D. Riedel
ICALP
2005
Springer
15 years 9 months ago
Logics for Unranked Trees: An Overview
Labeled unranked trees are used as a model of XML documents, and logical languages for them have been studied actively over the past several years. Such logics have different purpo...
Leonid Libkin
EUROCAST
2007
Springer
133views Hardware» more  EUROCAST 2007»
15 years 7 months ago
Temporal Equilibrium Logic: A First Approach
In this paper we introduce an extension of Equilibrium Logic (a logical characterisation of the Answer Set Semantics for logic programs) consisting in the inclusion of modal tempor...
Pedro Cabalar, Gilberto Pérez Vega
119
Voted
OOPSLA
2010
Springer
15 years 1 months ago
Modular logic metaprogramming
In logic metaprogramming, programs are not stored as plain textfiles but rather derived from a deductive database. While the benefits of this approach for metaprogramming are ob...
Karl Klose, Klaus Ostermann
LOPSTR
2009
Springer
15 years 10 months ago
Goal-Directed and Relative Dependency Pairs for Proving the Termination of Narrowing
In this work, we first consider a goal-oriented extension of the dependency pair framework for proving termination w.r.t. a given set of initial terms. Then, we introduce a new re...
José Iborra, Naoki Nishida, Germán V...