Sciweavers

8766 search results - page 487 / 1754
» Functional logic programming
Sort
View
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
15 years 8 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
15 years 8 months ago
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currentl...
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
LICS
2007
IEEE
15 years 10 months ago
First-Order and Temporal Logics for Nested Words
Nested words are a structured model of execution paths in procedural programs, reflecting their call and return nesting structure. Finite nested words also capture the structure ...
Rajeev Alur, Marcelo Arenas, Pablo Barceló,...
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
15 years 8 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski
FAC
2008
114views more  FAC 2008»
15 years 4 months ago
Specification of communicating processes: temporal logic versus refusals-based refinement
Abstract. In this paper we consider the relationship between refinement-oriented specification and specifications using a temporal logic. We investigate the extent to which one can...
Gavin Lowe