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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 5 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
BMAS
2000
IEEE
15 years 6 months ago
High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A
System design requires experienced designers that use heuristics and built up knowledge to propose a high order solution. Behavioral models can help to formalise, optimise and spe...
Erik Lauwers, Georges G. E. Gielen, Koen Lampaert,...
108
Voted
DATE
2006
IEEE
90views Hardware» more  DATE 2006»
15 years 7 months ago
Microarchitectural floorplanning under performance and thermal tradeoff
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...
Michael B. Healy, Mario Vittes, Mongkol Ekpanyapon...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
15 years 10 months ago
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
Ansgar Stammermann, Domenik Helms, Milan Schulte, ...
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
15 years 7 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...