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DAC
2005
ACM
13 years 8 months ago
Piece-wise approximations of RLCK circuit responses using moment matching
Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there...
Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 6 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
13 years 10 months ago
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
IESS
2007
Springer
156views Hardware» more  IESS 2007»
14 years 12 days ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspeciļ¬c architectures...
Jelena Trajkovic, Daniel Gajski
DAC
2009
ACM
14 years 7 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...