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150
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VTS
2002
IEEE
113views Hardware» more  VTS 2002»
15 years 9 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
134
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ASPDAC
2009
ACM
141views Hardware» more  ASPDAC 2009»
15 years 9 months ago
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri...
172
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CINQ
2004
Springer
157views Database» more  CINQ 2004»
15 years 8 months ago
Inductive Databases and Multiple Uses of Frequent Itemsets: The cInQ Approach
Inductive databases (IDBs) have been proposed to afford the problem of knowledge discovery from huge databases. With an IDB the user/analyst performs a set of very different operat...
Jean-François Boulicaut
LREC
2010
225views Education» more  LREC 2010»
15 years 6 months ago
C-3: Coherence and Coreference Corpus
The phenomenon of coreference, covering entities, their mentions and their properties, is intricately linked to the phenomenon of coherence, covering the structure of rhetorical r...
Cristina Nicolae, Gabriel Nicolae, Kirk Roberts
ERSA
2006
119views Hardware» more  ERSA 2006»
15 years 6 months ago
Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment
Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MPSoC) platform is a challenging task. Having FPGA fabric tiles in such MPS...
Vincent Nollet, Prabhat Avasare, Diederik Verkest,...