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CODES
2009
IEEE
15 years 11 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
179
Voted
BMCBI
2008
126views more  BMCBI 2008»
15 years 6 months ago
c-REDUCE: Incorporating sequence conservation to detect motifs that correlate with expression
Background: Computational methods for characterizing novel transcription factor binding sites search for sequence patterns or "motifs" that appear repeatedly in genomic ...
Katerina Kechris, Hao Li
193
Voted
BMCBI
2005
135views more  BMCBI 2005»
15 years 6 months ago
A robust two-way semi-linear model for normalization of cDNA microarray data
Background: Normalization is a basic step in microarray data analysis. A proper normalization procedure ensures that the intensity ratios provide meaningful measures of relative e...
Deli Wang, Jian Huang, Hehuang Xie, Liliana Manzel...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 6 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
ESTIMEDIA
2006
Springer
15 years 9 months ago
Design of a WCET-Aware C Compiler
This paper presents techniques to tightly integrate worstcase execution time (WCET) information into a compiler framework. Currently, a tight integration of WCET information into ...
Heiko Falk, Paul Lokuciejewski, Henrik Theiling