138 search results - page 28 / 28 » Functional test generation for delay faults in combinational... |
98
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DAC
2008
ACM
16 years 18 days ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
102
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TCAD
1998
14 years 11 months ago
1998
Abstract—We examine the implications of a new hazard-free combinational logic synthesis method [1], which generates multiplexor-based networks from binary decision diagrams (BDDs...
104
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DAC
2001
ACM
16 years 17 days ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...