138 search results - page 9 / 28 » Functional test generation for delay faults in combinational... |
EURODAC
1995
IEEE
15 years 1 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
55
Voted
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
83
Voted
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
78
Voted
TCAD
2002
14 years 9 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only re...