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» Functional test generation for non-scan sequential circuits
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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
15 years 6 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
MEMOCODE
2007
IEEE
15 years 4 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
15 years 2 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
ERLANG
2004
ACM
15 years 3 months ago
Flow graphs for testing sequential Erlang programs
Testing of software components during development is a heavily used approach to detect programming errors and to evaluate the quality of software. Systematic approaches to softwar...
Manfred Widera
GECCO
2003
Springer
148views Optimization» more  GECCO 2003»
15 years 2 months ago
Structural and Functional Sequence Test of Dynamic and State-Based Software with Evolutionary Algorithms
Evolutionary Testing (ET) has been shown to be very successful for testing real world applications [10]. The original ET approach focusesonsearching for a high coverage of the test...
André Baresel, Hartmut Pohlheim, Sadegh Sad...