142 search results - page 13 / 29 » Functional test generation for non-scan sequential circuits |
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
VTS
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
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EVOW
1999
Springer
15 years 2 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
TC
1998
14 years 9 months ago
1998
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...