142 search results - page 20 / 29 » Functional test generation for non-scan sequential circuits |
ATS
2003
IEEE
15 years 3 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
ESSCIRC
2011
13 years 9 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
STOC
2005
ACM
15 years 10 months ago
2005
ACM
We investigate constructions of pseudorandom generators that fool polynomial tests of degree d in m variables over finite fields F. Our main construction gives a generator with se...
VTS
2000
IEEE
15 years 2 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...