Sciweavers

142 search results - page 21 / 29
» Functional test generation for non-scan sequential circuits
Sort
View
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 2 months ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
VTS
1999
IEEE
114views Hardware» more  VTS 1999»
15 years 2 months ago
Partial Scan Using Multi-Hop State Reachability Analysis
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
Sameer Sharma, Michael S. Hsiao
VLSI
2007
Springer
15 years 3 months ago
Impact of hardware emulation on the verification quality improvement
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
Youssef Serrestou, Vincent Beroulle, Chantal Robac...
VLSID
2005
IEEE
120views VLSI» more  VLSID 2005»
15 years 3 months ago
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattachar...
TCAD
2008
114views more  TCAD 2008»
14 years 9 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty