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» Functional test generation for non-scan sequential circuits
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VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
15 years 10 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...
DATE
1999
IEEE
102views Hardware» more  DATE 1999»
15 years 2 months ago
Minimal Length Diagnostic Tests for Analog Circuits using Test History
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
Alfred V. Gomes, Abhijit Chatterjee
JISE
2000
68views more  JISE 2000»
14 years 9 months ago
Testable Path Delay Fault Cover for Sequential Circuits
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Ch...
ATS
2000
IEEE
145views Hardware» more  ATS 2000»
15 years 2 months ago
Compaction-based test generation using state and fault information
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwa...