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» Functional test generation for non-scan sequential circuits
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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 2 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
ICCD
2006
IEEE
127views Hardware» more  ICCD 2006»
15 years 6 months ago
Power Droop Testing
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd...
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
15 years 2 months ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
15 years 1 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
TODAES
1998
64views more  TODAES 1998»
14 years 9 months ago
Functional test generation for delay faults in combinational circuits
Irith Pomeranz, Sudhakar M. Reddy