142 search results - page 5 / 29 » Functional test generation for non-scan sequential circuits |
FPGA
1997
ACM
15 years 1 months ago
1997
ACM
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
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ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
ICCAD
1998
IEEE
15 years 2 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
DATE
1998
IEEE
15 years 2 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...