The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...